1. Field of the Invention
The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to a method of controlling barrier metal polishing processes based upon x-ray fluorescence measurements.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
In modem integrated circuit devices, millions of transistors are formed above a surface of a semiconducting substrate. To perform their intended functions, these transistors, or groups of transistors, are electrically coupled together by many levels of conductive inter-connections, i.e., conductive metal lines and plugs. These conductive lines and plugs allow electrical signals to propagate throughout the integrated circuit device. In general, these conductive interconnections are formed in layers of insulating material, e.g., silicon dioxide, HSQ, or other materials that may have a dielectric constant less than approximately 4. The insulating materials electrically isolate the various conductive interconnections and tend to reduce capacitive coupling between adjacent metal lines when the integrated circuit device is in operation.
As the demand for high performance integrated circuit devices continues to increase, circuit designers and manufacturers look for ways to improve device performance. Recently, copper has become the material of choice for conductive interconnections for high performance integrated circuit devices, e.g., microprocessors, due to its lower resistance as compared to, for example, aluminum.
Conductive interconnections comprised of copper may be formed using a variety of process flows, e.g., single damascene, dual damascene, etc. For example, a layer of insulating material may be formed on or above a semiconducting substrate. Thereafter, a plurality of openings may be formed in the layer of insulating material using known photolithographic and etching techniques. Then, a relatively thin barrier metal layer comprised of, for example, tantalum, is conformally deposited above the insulating layer and in the openings in the insulating layer. Next, a relatively thin layer of copper, a so-called copper seed layer, is deposited on the barrier metal layer. A much thicker layer of copper is then formed by using known electroplating techniques. This final layer of copper will fill the remaining portions of the openings in the insulating layer, and have an upper surface that extends above the surface of the insulating layer.
Ultimately, one or more chemical mechanical polishing (CMP) operations will be performed to remove the excess copper and barrier layer material from above the surface of the insulating layer. This process results in the definition of a plurality of conductive inter-connections, e.g., conductive lines or plugs, or a combination of both, positioned within the openings in the insulating layer. Such chemical mechanical polishing operations may involve a sequence of polishing operations. For example, the bulk of the excess copper may be removed during an initial, timed polishing process. The removal rate during the initial timed polishing process may be relatively high. Thereafter, an endpoint polish process may be performed to remove the remaining copper material. The removal rate during this endpoint process may be relatively low. The endpoint of this portion of the process may be detected through use of an optical sensor, such as a laser-type system whereby the intensity of light reflected off of the wafer is measured. Additional polishing operations may be performed to remove the barrier layer material.
As set forth above, chemical mechanical polishing is an important process as it relates to the formation of conductive interconnections comprised of copper in modern integrated circuit devices. A variety of chemical mechanical polishing tools are commercially available. In all such systems, the object is to polish the surface of a process layer, e.g., copper, with a polishing pad in the presence of a polishing slurry. In general, chemical mechanical polishing involves the selective removal of all or portions of the process layer or film from the wafer through chemical reactivity of the polishing slurry used during the process, and the mechanical abrasion of the process layer due to its contact with the polishing pad. For example, the chemical component of the CMP process is dependent on the chemistry, concentration and pH of the polishing slurry. Furthermore, the mechanical abrasion is dependent on, among other things, the slurry particle size and concentration, polishing pad hardness and surface roughness, pad pressure, and the rotational speeds of the wafer and the pad. All of these variables tend to make accurately controlling CMP processes difficult.
As set forth above, the polishing of copper is typically accomplished in multistage polishing systems. For example, bulk copper removal (at relatively high rates) may be performed at a first stage, additional copper removal (at relatively slower rates) may be performed at a second stage, and a third stage may be used for removal of any underlying barrier layer material. However, due to the many variables encountered in CMP processes, the removal of the copper material may be less than complete across the entire surface of the wafer. More particularly, it is difficult to detect if all of the copper material has been removed before the wafers are moved to the polishing stage where it is intended that the barrier metal material be removed. More importantly, the existence of the residual copper may inhibit removal of the barrier layer material. Over-polishing in an attempt to insure that all of the copper is removed is undesirable in that it may result in an undesirable level of dishing of the resulting metal lines and otherwise produce across-wafer non-uniformities. Under-polishing can produce undesirable surface topographies and may lead to electrical shorts if sufficient quantities of residual copper remain above the insulating layer. Similarly, it is difficult to detect when all of the barrier metal layer has been removed by polishing. Over-polishing the barrier metal layer to insure complete removal of the barrier layer is undesirable in that it may lead to excessive erosion of the underlying insulating layer, and it may tend to reduce the thickness of the conductive interconnection beyond acceptable limits.
Additionally, in traditional CMP tools, after polishing operations are believed to be complete, the wafer is subjected to a post-CMP clean process and measured to determine if all of the layer under consideration, e.g., copper layer, barrier metal layer, was removed. If not, the incompletely polished wafer must be returned to the CMP tool for further polishing operations. All of these steps lead to increased product cycle times and reduced yields.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is directed to a method of controlling barrier metal polishing processes based upon x-ray fluorescence measurements. In one illustrative embodiment, the method comprises providing a wafer comprised of a layer of insulating material having a barrier metal layer formed thereabove, performing a chemical mechanical polishing operation to remove the barrier metal layer material from above the insulating layer, irradiating at least one area of the wafer with x-rays, and analyzing x-rays leaving the irradiated area to determine the presence of the barrier metal layer material. In a further embodiment, the method comprises examining an x-ray spectrum of the x-rays leaving the irradiated area for the presence of the barrier metal layer material.